/*----------------------------------------------------------------------
 *
 * Copyright 2009, Thomas Dejanovic.
 *
 * This is free software; you can redistribute it and/or modify it
 * under the terms of the GNU Lesser General Public License as
 * published by the Free Software Foundation; either version 2.1 of
 * the License, or (at your option) any later version.
 *
 * This software is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this software; if not, write to the Free
 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA, or see the FSF site: http://www.fsf.org.
 *
 *---------------------------------------------------------------------
 *
 * Simple design to sanotu test the serial port to apb bus interface
 * on the s3board form digilent:
 *  http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD
 *
 *---------------------------------------------------------------------*/


module s3board

  (/*AUTOARG*/
  // Outputs
  an, ssd, led, rxd_out, aux_rxd_out,
  // Inputs
  clk50, btn, swt, txd_in, aux_txd_in
  );

  //----------------------------------------
  input                 clk50;

  input [3:0]           btn;
  input [7:0]           swt;
  output [3:0]          an;
  output [7:0]          ssd;
  output [7:0]          led;
  //----------------------------------------

  //----------------------------------------
  // serial ports
  input                 txd_in;
  output                rxd_out;

  input                 aux_txd_in;
  output                aux_rxd_out;
  //----------------------------------------


  /*----------------------------------------------------------------*/

  /*-AUTOUNUSED-*/

  /*AUTOINPUT*/

  /*AUTOOUTPUT*/

  /*-AUTOREGINPUT-*/

  /*AUTOREG*/

  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire [3:0]            button_in;              // From core of s3board_core.v
  wire                  c0_inc;                 // From core of s3board_core.v
  wire [3:0]            c0_out;                 // From hatch of s3board_hatch.v
  wire                  c1_inc;                 // From core of s3board_core.v
  wire [3:0]            c1_out;                 // From hatch of s3board_hatch.v
  wire                  c2_inc;                 // From core of s3board_core.v
  wire [3:0]            c2_out;                 // From hatch of s3board_hatch.v
  wire                  c3_inc;                 // From core of s3board_core.v
  wire [3:0]            c3_out;                 // From hatch of s3board_hatch.v
  wire                  gated_pclk;             // From dcom of dcom_apb.v
  wire                  gated_pclk_en;          // From dcom of dcom_apb.v
  wire [7:0]            led_out;                // From hatch of s3board_hatch.v
  wire [29:0]           paddr;                  // From dcom of dcom_apb.v
  wire                  pclk;                   // From dcom of dcom_apb.v
  wire                  pclk_en;                // From dcom of dcom_apb.v
  wire                  penable;                // From dcom of dcom_apb.v
  wire [31:0]           prdata;                 // From hatch of s3board_hatch.v
  wire                  preset_l;               // From dcom of dcom_apb.v
  wire                  psel;                   // From dcom of dcom_apb.v
  wire [31:0]           pwdata;                 // From dcom of dcom_apb.v
  wire                  pwrite;                 // From dcom of dcom_apb.v
  wire                  reset;                  // From core of s3board_core.v
  wire [7:0]            switch_in;              // From core of s3board_core.v
  wire                  soft_reset_out;         // From hatch of s3board_hatch.v
  // End of automatics

  /*------------------------------------------------------------------
   *
   * local definitions and connections.
   *
   * */
  wire                  clk;
  wire                  clk_en;
  assign                clk    = clk50;
  assign                clk_en = 1'd1;

  wire                  aux_rxd_out;
  assign                aux_rxd_out = 1'd1;

  // 115200 @  50MHz =  53
  wire [7:0]            dcom_scaler;
  assign                dcom_scaler = 8'd53;

 /*-----------------------------------------------------------------
   *
   *
   *
   * */

  s3board_core core
    (/*AUTOINST*/
     // Outputs
     .reset                             (reset),
     .an                                (an[3:0]),
     .ssd                               (ssd[7:0]),
     .led                               (led[7:0]),
     .button_in                         (button_in[3:0]),
     .switch_in                         (switch_in[7:0]),
     .c3_inc                            (c3_inc),
     .c2_inc                            (c2_inc),
     .c1_inc                            (c1_inc),
     .c0_inc                            (c0_inc),
     // Inputs
     .clk50                             (clk50),
     .btn                               (btn[3:0]),
     .swt                               (swt[7:0]),
     .led_out                           (led_out[7:0]),
     .c3_out                            (c3_out[3:0]),
     .c2_out                            (c2_out[3:0]),
     .c1_out                            (c1_out[3:0]),
     .c0_out                            (c0_out[3:0]),
     .soft_reset_out                    (soft_reset_out));

  dcom_apb dcom
    (/*AUTOINST*/
     // Outputs
     .rxd_out                           (rxd_out),
     .pclk                              (pclk),
     .pclk_en                           (pclk_en),
     .gated_pclk                        (gated_pclk),
     .gated_pclk_en                     (gated_pclk_en),
     .preset_l                          (preset_l),
     .penable                           (penable),
     .psel                              (psel),
     .paddr                             (paddr[29:0]),
     .pwrite                            (pwrite),
     .pwdata                            (pwdata[31:0]),
     // Inputs
     .clk                               (clk),
     .clk_en                            (clk_en),
     .reset                             (reset),
     .txd_in                            (txd_in),
     .dcom_scaler                       (dcom_scaler[7:0]),
     .prdata                            (prdata[31:0]));

  s3board_hatch hatch
    (/*AUTOINST*/
     // Outputs
     .prdata                            (prdata[31:0]),
     .led_out                           (led_out[7:0]),
     .c3_out                            (c3_out[3:0]),
     .c2_out                            (c2_out[3:0]),
     .c1_out                            (c1_out[3:0]),
     .c0_out                            (c0_out[3:0]),
     .soft_reset_out                    (soft_reset_out),
     // Inputs
     .pclk                              (pclk),
     .pclk_en                           (pclk_en),
     .gated_pclk                        (gated_pclk),
     .gated_pclk_en                     (gated_pclk_en),
     .preset_l                          (preset_l),
     .penable                           (penable),
     .psel                              (psel),
     .paddr                             (paddr[29:0]),
     .pwdata                            (pwdata[31:0]),
     .pwrite                            (pwrite),
     .button_in                         (button_in[3:0]),
     .switch_in                         (switch_in[7:0]),
     .c3_inc                            (c3_inc),
     .c2_inc                            (c2_inc),
     .c1_inc                            (c1_inc),
     .c0_inc                            (c0_inc));

  /*----------------------------------------------------------------*/

endmodule // s3board


// Local Variables:
// verilog-library-directories:("." "../../modules/*")
// verilog-library-extensions:(".v")
// End:
